This invention relates to phase lock loops (PLLs). More specifically, this invention relates to monitoring and controlling the input voltages to the xe2x80x9cvoltage controlled oscillatorxe2x80x9d (VCO) for use in optimizing a PLL.
A PLL (Phase Lock Loop) is a basic design in communication chips. The PLL""s design goal is the generation of a clock with precise frequency and phase by control over a xe2x80x9cVCOxe2x80x9d block (Voltage Controlled Oscillator) that is part of the PLL.
The smaller the xe2x80x9cVCO gainxe2x80x9d (the ratio of additional voltage vs. additional frequency) is, the better is the precision of the control over the VCO and frequency. Additionally, reduced VCO gain improves resistance to noise as well, because a small range of frequency is relating to a wide range of voltage (i.e. a major change in the input voltage will produce only a minor adjustment in the frequency).
In order to utilize narrow bands of voltage level in the circuit (i.e. a reasonable range of 10 millivoltsxe2x88x921 volt), the design should be one wherein the launch value of the frequency fits the narrow range where the desired frequency is. Due to inherent inconsistencies in manufacturing procedures or raw material qualities, the initial frequency obtained may vary, thus the range of voltage cannot be as narrow as could ideally be wished for.
As the VCO gain is reduced, the variation over the input voltage gets larger in order to maintain the same frequency range. Large variation over the input voltage creates a large distortion of operation in the other control circuits in the PLL, and makes the design of those circuits more difficult.
Therefore there is a need in the art for PLL circuits in which the required voltage range can be narrowed without losing the flexibility of achieving a narrow VCO gain.
Therefore, it is an object of the present invention to provide a PLL with a compensation circuit which is less sensitive to input voltage changes.
It is a further object of the present invention to provide a PLL with a compensation circuit permitting one to obtain as small a VCO gain as desired, while maintaining the minimum voltage range needed.
It is a further objective of the compensation circuit of the present invention, to produce a resultant reduction in the number of communications chips which are produced that are unacceptable due to the disparity between the initial frequency and the desired frequency range.
Those objectives and others not mentioned hereinabove are achieved by the present invention in which a compensation circuit monitors the input voltage to the VCO. When the monitored voltage reaches a certain predetermined and/or selectable level (as large as one""s control circuit is designed to tolerate) the circuit automatically steps the VCO (i.e. changes the range of the frequency) up by one step and lowers the voltage back to its base level. This procedure can be repeated until the desired frequency is achieved.
Using the exemplary embodiments described hereinbelow provides one skilled in the art to control VCOs over a very large frequency range, as much as 10%-15% of the tuning frequency/process, using a very small voltage range, from 10 millivolts to as much as 1 Volt. Particularly, in PLL circuits, the range of frequency may be from 10%-50% tuning frequency over process.